CMOS Implementation of a Piecewise Linear Activation Function Based Neuron Unit for Neural Network Accelerator

In this research, the architecture of a piecewise linear (PL) activation function based Neuron Unit for Neural Network Accelerator has been proposed. The Neuron Unit is designed and simulated in CMOS 90 nm process. At first, a 4*4 Array multiplier is designed, followed by a 10-bit register unit to implement a MAC unit. A 10-bit digital Magnitude Comparator circuit is being used to implement the PL activation function. The PL activation function, along with a Neuron Response Register and the MAC unit completes the overall architecture of the proposed Neuron Unit. The design has 100% accuracy with 18.75 pJ energy and 28.85 μW power consumption.