Performance Enhancement of Conventional Design of 4-Bit Carry Look-Ahead Adder

This research aims to increase performance parameters of conventional CMOS based 4-bit carry look-ahead (CLA) adder. CLA adder in conventional design fully utilize static CMOS (S-CMOS) logic for which its transistor count is quite high. Moreover, due to high input impedance, its delay is also high. To enhance performance and to reduce transistor count, (1) full swing gate diffusion input (GDI) based AND gates and (2) GDI based XOR gates have been utilized rather than using S-CMOS based AND and XOR gates. According to simulation conducted using Cadence tools, the proposed CLA adder design achieved noteworthy improvements in performance compared to the fully S-CMOS based existing design.