Low Power Design of a Two Bit Mangitude Comparator for High Speed Operation

Binary magnitude comparator is considered as an elementary apparatus in Arithmetic Logic Unit. Due to increased use of portable devices nowadays, energy efficient designs having less delay have become essential. This research introduces a new two-bit binary magnitude comparator consisting 46 transistors. To analyze performance, simulation of the proposed design has been conducted using Cadence Computer Aided Design apparatus in 90 nm Technology. To analyze design feasibility, the proposed design has been compared with the existing two-bit binary magnitude comparator design. According to simulation result, the proposed design displayed 9.865 $\mu$ W average power consumption, 0.193 ns delay and 1.904 fJ Power Delay Product which was significantly less than the existing two-bit magnitude comparator designs.