A 9-to-13 GHz CPPLL with -72.27 dBc reference spur, 80.9 fs<sub>rms</sub> jitter and -246.9 dB FoM in 65-nm CMOS process

The growth in 5G mm-Wave communications draws tremendous demands on the high-quality signal sources. To satisfy the requirements for a wide tuning range and low phase noise, PLL cascaded with a frequency multiplier is typically applied in mm-Wave systems. In this letter, a 9-13 GHz integer-N charge-pump PLL (CPPLL) is designed, which could cooperate with a frequency tripler and a 6-GHz intermediate frequency to fully cover the 5G mm-wave FR2 frequency bands. In the PLL design, a parallel inductor is used in the voltage-controlled oscillator (VCO) to avoid its Q-factor degradation, thus improving the phase noise performance. Additionally, thick-oxide transistors are employed to extend the CP output voltage range, which could increase the PLL tuning range with a relatively small…